Interconnection Networks for Scalable Quantum Computers

We show that the problem of communication in a quantum computer reduces to constructing reliable quantum channels by distributing high-fidelity EPR pairs. We develop analytical models of the latency, bandwidth, error rate and resource utilization of such channels, and show that 100s of qubits must be distributed to accommodate a single data communication. Next, we show that a grid of teleportation nodes forms a good substrate on which to distribute EPR pairs. We also explore the control requirements for such a network. Finally, we propose a specific routing architecture and simulate the communication patterns of the Quantum Fourier Transform to demonstrate the impact of resource contention.Comment: To appear in International Symposium on Computer Architecture 2006 (ISCA 2006

Automated Generation of Layout and Control for Quantum Circuits

We present a computer-aided design flow for quantum circuits, complete with automatic layout and control logic extraction. To motivate automated layout for quantum circuits, we investigate grid-based layouts and show a performance variance of four times as we vary grid structure and initial qubit placement. We then propose two polynomial-time design heuristics: a greedy algorithm suitable for small, congestionfree quantum circuits and a dataflow-based analysis approach to placement and routing with implicit initial placement of qubits. Finally, we show that our dataflow-based heuristic generates better layouts than the state-of-the-art automated grid-based layout and scheduling mechanism in terms of latency and potential pipelinability, but at the cost of some area.

Can we build classical control circuits for silicon quantum computers? 2nd Workshop on Non-Silicon Computation

Many who propose quantum computing technologies focus on the quantum datapath without addressing the complexity of the classical control. We investigate the complexity of control for a specific technology, namely the Kane silicon quantum computer. We show that the pulse sequences required to effect one of the simplest operations – two-bit swap – poses a significant challenge to scalable implementation. The reason for this is two-fold: first, extremely cold operating temperatures require use of something other than CMOS for control and, second, pulse-generation for a single bit in the datapath requires many classical transistors. The result suggests that architects must focus on a form of SIMD for quantum datapaths, sharing pulse-generation circuits between as many quantum bits as possible. 1